This invention relates to a discrete-time signal processing system comprising a signal sampling circuit and a sampling signal generator whose sampling frequency is adjustable, the sampling signal generator including an oscillator for generating a signal which has a fixed frequency, and a frequency divider.
In discrete-time signal processing circuits the sampling frequency for sampling an analog or digital input signal to be processed is often generated by converting, by means of a frequency divider, a high-frequency output signal of an oscillator into a sampling signal (clock signal) having a lower frequency. Needless to observe that the oscillation frequency of the oscillator should to be accurate and stable, which is mostly achieved by the use of a crystal oscillator. The above means that the sampling frequencies are restricted to f.sub.osc /n where f.sub.osc is the oscillation frequency and n the dividend of the frequency divider. If the oscillation frequency f.sub.osc is relatively low compared to the clock frequency, this denotes that the clock frequency can be adjusted only in coarse steps. Conversely, if a specific clock frequency is desired, the choice of the frequency, divider will then determine the oscillation frequency which in many cases does not correspond to the frequencies of the oscillator crystals which are commercially available (and thus cost effective). Furthermore, it may happen that more than one sampling frequency is necessary, such as, for example, in sampling frequency converters. This would require two (precision) oscillators, which is more expensive and more cumbersome compared to a circuit comprising a single oscillator.